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TDA9206
I2C BUS CONTROLLED 130MHz RGB PREAMPLIFIER
. . . . . . . . . .
130MHz TYPICAL BANDWIDTH AT 2VPP OUTPUT WITH 12pF CAPACITIVE LOAD 2.8ns TYPICAL RISE/FALL TIME AT 2VPP OUTPUT WITH 12pF CAPACITIVE LOAD POWERFULL OUTPUT DRIVE CAPABILITY BRT, CONT, DRIVE, OUTPUT DC LEVEL, OSD CONTRAST, BACK-PORCH CLAMPING PULSE WIDTH ARE I2C BUS CONTROLLED INTERNAL BACK-PORCH CLAMPING PULSE GENERATOR OSD WHITE BALANCE TRACKING INTERNAL OSD SWITCHES BLANKING AND FAST-BLANKING INPUTS VERY LARGE DRIVE ADJUSTMENT RANGE (48dB) SEMI-TRANSPARENT BACKGROUND ON OSD PICTURE
DIP24 (Plastic Package) ORDER CODE : TDA9206
PIN CONNECTIONS
IN1 OSD1
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
HSYNC PVCC1 OUT1 PGND1 PVCC2 OUT2 PGND2 PVCC3 OUT3 PGND3 BLK FBLK
9206-01.EPS
DESCRIPTION The TDA9206 is a digitaly controlled wideband video preamplifier intended for use in high resolution color monitor. All controls and adjustments are digitaly performed thanks to I2C serial bus. Contrast, brightness and DC output level of RGB signals are common to the 3 channels and drive adjustment is separate for each channel. Three I2C gain controlled OSD inputs can be switched with RGB signals using fast blanking command. Clamping of RGB signals is performed thanks to a flexible integrated system. The white balance adjustment is effective on brightness, video and OSD signals. The TDA9206works for application usingAC or DC coupled CRT driver. Because of its features and due to component saving the TDA9206 leads to a very performantand cost effective application.
September 1996
AVDD IN2 OSD2 AGND IN3 OSD3 LVDD LGND SDA SCL
1/12
TDA9206
PIN DESCRIPTION
Name IN1 OSD1 AVDD IN2 OSD2 AGND IN3 OSD3 LVDD LGND SDA SCL Pin 1 2 3 4 5 6 7 8 9 10 11 12 Type I I I I I I/O I I I I/O I/O I
st
Function 1 Channel Main Picture Input 1st Channel OSD Input 12V Analog VDD 2 2
nd nd
Name FBLK BLK PGND3 OUT3 PVCC3 PGND2 OUT2 PVCC2 PGND1 OUT1 PVCC1 HSYNC
Pin 13 14 15 16 17 18 19 20 21 22 23 24
Type I I I/O O I I/O O I I/O O I I
Function Fast Blanking Input Blanking Input 3rd Channel Power Ground 3 Channel Output 3 Channel Power VCC 2nd Channel Power Ground 2 2
nd nd rd rd
Channel Main Picture Input Channel OSD Input
Analog Ground 3 Channel Main Picture Input 3 Channel OSD Input 12V Logic VDD Logic Ground Serial Data Line Serial Clock Line
rd rd
Channel Output Channel Power VCC
1st Channel Power Ground 1 Channel Output 1 Channel Power VCC Horizontal Synch Input
st
9206-01.TBL 9206-02.EPS
st
BLOCK DIAGRAM
BLK
14
FBLK
13
P VCC1
23
CLAMP VREF
3 1
BRIGHTNESS DRIVE
BP C P
CO NTRAST
AVDD IN1 AGND
OUTPUT STAGE
22 OUT1 21 PGND1
6
8 bits IN2
4
20 PVCC2 19 OUT2 18 PGND2
BLUE CHANNEL
IN3 LVDD
7 9
GREEN C HANNEL
16 OUT3 17 PVCC3
LGND 10
BP CP
15 PGND3
LATCHES I2 C D/A BUS DECODER
OSD CONT I2 C VREF
O UTPUT DC LEVEL ADJ US T
TDA9206
24 11 12 2 5 8
HS YNC
SDA
SCL
OSD1
OSD2
OSD3
2/12
TDA9206
FUNCTIONAL DESCRIPTION Input Stage The R, G and B signals must be fed to the three inputs through coupling capacitors (100nF). The maximum input peak-to-peak video amplitude is 1V. The input stage includes a clamping function. This clamp is using the input serial capacitor as "memory capacitor" and is gated by an internally generated "Back-Porch-Clamping-Pulse (BPCP)". The synchronization edge of the BPCP is selected according bit 0 of register R8. When B0R8 is set to 1, the BPCP is synchronized on the leading edge of the blanking pulse BLK inputs on Pin 14 (see Figure 1). Figure 1
BLK HSYNC BPCP
9206-04.EPS 9206-05.EPS
This DC-Offset is present only outside the blanking pulse (see Figure 3). The DC output level during the blanking pulse, is forced to "INFRA-BLACK" level (VDC). Drive Adjustment (3 x 8 bits) In order to adjust the white balance , the TDA9206 offers the possibility to adjust separately the overall gain of each complete video channel. The gain of each channel is controlled by I2C (8bits each). The very large drive adjustment range (48dB) allows different standard or custom color temperature. It can also be used to adjust the output voltages at the optimum amplitude to drive the C.R.T drivers, keeping the whole contrast control for end-user only. The drive adjustment is located after the CONTRAST, BRIGHTNESS and OSD switch blocks, so that the white balance will remains correct when BRT is adjusted, and will also be correct on OSD portion of the signal. OSD Inputs The TDA9206 includes all the circuitry necessary to mix OSD signals into the RGB main-picture. Four pins are dedicated to this function as follow. Three TTL RGB On Screen Display inputs (Pin 2, 5 and 8). These three inputs are connected to the three outputs of the corresponding ONSCREEN-DISPLAY processor (ex : STV942x). One Fast Blanking Input (FBLK, Pin 13) which is also connected to the FBLK output of the same ON-SCREEN-DISPLAY processor. When a high level is present on FBLK, the IC will acts as follow : - The three main picture RGB input signals are internally switched to the internal input clamp reference voltage. - The three output signals are set to voltages corresponding to the state (0 or 1) on the three OSD inputs (see Figure 3). Example : If FBLK = 1 and OSD1, OSD2, OSD3) = 1, 0, 1 respectively. Then OUT1, OUT2, OUT3 will be equal to VOSD, VBRT, VOSD, where : VBRT = VBLACK + BRT VOSD = VBRT + OSD BRT is the brightness DC level I2C adjustable. OSD is the On-Screen Display signal value I2C adjustable from 0V to 4.68VPP by step of 0.312V. Semi-transparent function is controlled thanks to Bit 6 of R8 register (see Table 1). When semi-transparent mode is activated, video signal is divided by 2 (CONT).
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Internal pulse width is controlled by I C
2
When B0R8 is clear to 0, the BPCP is synchronized on the second edge of the horizontal pulse HSYNC inputs on Pin 24. An automatic function allows to use positive or negative horizontal pulse on Pin 24 (see Figure 2). Figure 2
HSYNC
BPCP
Internal pulse width is controlled by I2C
In both case BPCP width is adjustable by I 2C, B1 and B2 of register R8 (see R8 Table P8). Contrast Adjustment (8 bits) The contrast adjustment is made by controlling simultaneously the gain of three internal variable gain amplifiers through the I2C bus interface. The contrast adjustment allows to cover a typical range of 48dB. Brightness Adjustment (8 bits) As for the contrast adjustment, the brightness is controlled by I2C. The brightness function consists to add the same DC offset to the three R, G, B signals after contrast amplification.
TDA9206
FUNCTIONAL DESCRIPTION (continued) Table 1
FBLK OSD1 OSD2 OSD3 B6R8 0 1 0 1 1 1 1 x x x 0 x x 1 x x x x 1 x 0 x x x x x 0 1 0 0 1 1 1 1 1 Output Signal (OUTn) Video OSD (1) Video OSD OSD OSD Semi-transparent (2)
- The output CLAMP : The IC also incorporates three internal output clamp (sample and hold system) which allow to DC shift the three output signals. The DC output voltage is adjustable through I2C with 4 bits. Practicaly, the DC output level allow to adjust the BLK level (VDC = 400mV under VBLACK) from 0.9V to 2.9V with 12 x 165mV. The overall waveforms of the output signal according to the different adjustment are shown in Figures 3 and 4. Serial Interface The 2-wires serial interface is an I2C interface. The slave address of the TDA9206 is DC (in hexadecimal).
A6 1 A5 1 A4 0 A3 1 A2 1 A1 1 A0 0 W 0
Notes : 1. All OSD colors are displayed. 2. One OSD color is displayed as semi-transparent video without effect on brightness and DC level adjustment.
Output Stage The three output stages incorporate three functions which are : - The blanking stage : When high level is applied to the BLK input (Pin 14), the three outputs are switched to a voltage which is 400mV lower than the BLACK level. The black level is the output voltage with minimum brightness when input signal video amplitude is equal to "0". - The output stage itself : It is a large bandwidth output amplifier which allow to deliver up to 5VPP on the three outputs (for 0.7V video signal on the inputs). The typical bandwidth is 100MHz at -3dB measured with 4VPP output signal on 12pF load. Figure 3 : Waveforms VOUT, BRT, CONT, OSD
HSYNC BPCP BLK Video IN FBLK OSD IN
Data Transfer The host MCU can write data into the TDA9206 registers. Read mode is not available. To write data into the TDA9206, after a start, the MCU must send (see Figure 5) : - The I2C address slave byte with a low level for the R/W bit. - The byte of the internal register address where the MCU wants to write data(s). - The data. All bytes are sent MSB bit first and the write data transter is closed by a stop.
VOUT1, VOUT2, VOUT3 VCONT
(4)
VOSD (5) VBRT (3) VBLACK VDC (1)
(2)
OSD
CONT BRT 0.4V fixed
4/12
9206-06.EPS
Notes : 1. 2. 3. 4. 5.
VDC = 0.5 to 2.5V VBLACK = VDC + 0.4V VBRT = VBLACK + BRT (with BRT = 0 to 2.5V) V CONT = VBRT + CONT with CONT = k x Video IN (CONT = 5VPP max. for VIN = 0.7VPP) VOSD = VBRT + OSD with OSD = k1 x OSDIN (OSD max. = 5VPP, OSD min. = 312mVPP)
TDA9206
FUNCTIONAL DESCRIPTION (continued) Figure 4 : Waveforms (DRIVE adjustment)
HSYNC BPCP BLK Video IN FBLK OSD IN
VOUT1, VOUT2, VOUT3 VCONT VOS D VBRT VBLACK VDC Two examples of drive adjus tment (1)
9206-07.EPS
Note : 1. Drive a djus tm ent modifies the following voltage s : VCONT, VBRT and VO S D. Drive a djus tm ent do not modify the following voltage s : VDC a nd VBLACK.
Figure 5 : I2C Write Operation
SCL SDA Start I2C Slave Address W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK D7 D6 D5 D4 D3 D2 D1 D0 ACK Stop
9206-08.EPS 9206-02.TBL
Register Address
Data Byte
QUICK REFERENCE DATA
Symbol Parameter Signal Bandwidth (2VPP/12pF load) Rise and Fall Time (2VPP/12pF load) Drive Adjustment Range on the 3 Channels separately Maximum Output Voltage (V IN = 0.7 VPP) Output Voltage Range (AC + DC) Min. Typ. 130 2.8 48 5 8 Max. Unit MHz ns dB V V
5/12
TDA9206
ABSOLUTE MAXIMUM RATINGS
Symbol VS VIN1 VIN2 VESD Tstg Tj Toper Parameter Supply Voltage (Pins 3-9-17-20-23) Voltage at any Input Pins (except SDA & SCL) Voltage at any Input Pins (on SDA & SCL) ESD Susceptability (Human body model ; 100pF Discharge through 1.5k) Storage Temperature Junction Temperature Operating Temperature Value 14 GND < VIN1 < VS GND < VIN2 < 5.5 2 - 40, + 150 150 0, + 70 Unit V V V kV C C
9206-03.TBL 9206-06.TBL 9206-05.TBL 9206-04.TBL
C
THERMAL DATA
Symbol R th (j-a) Parameter Junction-ambient Thermal Resistance Value 62 Unit
o
C/W
DC ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, unless otherwise specified)
Symbol VS IS VI VO VIL OSD VIH OSD Supply Voltage Supply Current (All VS Pin current) Video Input Voltage Amplitude Typical Output Voltage Range Low Level Inputs OSD, FBLK, BLK, HSYNC High Level Inputs OSD, FBLK, BLK, HSYNC Parameter Test Conditions Pins 3-9-17-20-23 R L = 1k Pins 1-4-7 Pins 16-19-22 Pins 2, 5, 8, 13, 14, 24 Pins 2, 5, 8, 13, 14, 24 2.4 0.5 Min. 11.4 Typ. 12 90 0.7 1 8 0.8 Max. 12.6 Unit V mA VPP V V V
AC ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, CL = 12pF, RL = 1k , unless otherwise specified)
Symbol AV CAR DAR GM BW Bandwidth Large Signal Bandwidth Small Signal DIS tR, tF Video Output Distorsion (see Note) Video Output Rise and Fall Time (see Note) Parameter Maximum Gain (20 log x VOUT AC/VIN AC) Contrast Attenuation Range Drive Attenuation Range Gain Match Test Conditions Contrast & Drive at maximum VIN = 0.7V, BRT, Drive = POR VIN = 0.7V, Contrast, Drive = POR VOUT = 2.5VPP, VIN = 0.7VPP Contrast = Drive = Maxi x 0.7 (POR) At -3dB, VIN = 0.7VPP VOUT = 4VPP, Contrast = Drive = Maxi x 0.87 VOUT = 2VPP, Contrast = Drive = Maxi x 0.62 f = 1MHz, VOUT = 1VPP, VIN = 1VPP VIN = 0.7VPP, VOUT = 4VPP Contrast = Drive = Maxi x 0.87 VOUT = 2VPP Contrast = Drive = Maxi x 0.62 Min. Typ. 18 48 48 0.1 Max. Unit dB dB dB dB
100 130 0.3 3.8 2.8 2.5 0 4.5
MHz MHz % ns ns V V mV
BRT BRTM
Brightness Maximum DC Level Brightness Minimum DC Level Brightness Matching BRT = 50%, Drive = POR
20
Note : POR = Power-on Reset Value
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TDA9206
AC ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, CL = 12pF, RL = 1k , unless otherwise specified)
Symbol OSD CAR DC RL CT Parameter Contrast Attenuation Range for OSD Input Output Maximum DC Level Output Minimum DC Level Equivalent Load on Video Output Croostalk between Video Channels (see Note 1) with Tj Tj Max. VOUT = 2.5VPP, VIN = 0.7VPP Contrast = Drive = Maxi x 0.7 (POR) fIN = 1MHz fIN = 50MHz 0.47 Test Conditions Min. Typ. 24 2.5 0.5 1 Max. Unit dB V V k
9206-07.TBL 9206-09.EPS 9206-09.TBL 9206-08.TBL
44 34
dB dB
Notes : 1. 2.
These parameters are not tested on each unit. They are measured during an internal qualification procedure which includes characterization on batches coming from corners of our processes and also from temperature characterization. POR = Power-on Reset Value
I2C ELECTRICAL CHARACTERISTICS (Tamb = 25oC, VCC = 12V, unless otherwise specified)
Symbol VIL VIH IIN fSCL(Max.) VOL Parameter Low Level Input Voltage High Level Input Voltage Input Current SCL Maximum Clock Frequency Low Level Output Voltage SDA Pin when ACK Sink Current = 6mA 0.4V < VIN < 4.5V Test Conditions On Pins SDA, SCL 3 -10 200 0.6 +10 Min. Typ. Max. 1.5 Unit V V A kHz V
I2C INTERFACE TIMINGS REQUIREMENTS (See Figure 6)
Symbol tBUF tHDS tSUP tLOW tHIGH tHDAT tSUDAT tR, tF Parameter Time the bus must be free between 2 access Hold Time for Start Condition Set-up Time for Stop Condition The Low Period of Clock The High Period of Clock Hold Time Data Set-up Time Data Rise and Fall Time of both SDA and SCL Min. 1300 600 600 1300 600 300 250 20 300 Typ. Max. Unit ns ns ns ns ns ns ns ns
Figure 6
tBUF
SDA
tHDAT
tHDS
SCL
tSUDAT
tSUP
tHIGH
tLOW
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TDA9206
REGISTER DESCRIPTION Registers Sub-address
Address (Hex) 01 02 03 04 05 06 07 08 Register Names Contrast Brightness Drive 1 Drive 2 Drive 3 Output DC Level OSD Contrast BP and Miscellaneous Function DAC 8-bit DAC 8-bit DAC 8-bit DAC 8-bit DAC 8-bit DAC 4-bit DAC 4-bit See R8 Table POR Value B4 B4 B4 B4 B4 08 08 04
Contrast Register (R1) (Video IN = 0.5VPP, Brightness at minimum,Drive at maximum)
Hex 00 01 02 04 08 10 20 40 80 B4 FF b7 0 0 0 0 0 0 0 0 1 1 1 b6 0 0 0 0 0 0 0 1 0 0 1 b5 0 0 0 0 0 0 1 0 0 1 1 b4 0 0 0 0 0 1 0 0 0 1 1 b3 0 0 0 0 1 0 0 0 0 0 1 b2 0 0 0 1 0 0 0 0 0 1 1 b1 0 0 1 0 0 0 0 0 0 0 1 b0 0 1 0 0 0 0 0 0 0 0 1 CONT (VPP) 0 0.015 0.031 0.062 0.125 0.25 0.5 1 2 2.812 4 G (dB) -30 -24 -18 -12 -6 0 6 12 15 18 X POR Value
Brightness Register (R2) (Drive at maximum)
Hex 00 01 02 04 08 10 20 40 80 B4 FF b7 0 0 0 0 0 0 0 0 1 1 1 b6 0 0 0 0 0 0 0 1 0 0 1 b5 0 0 0 0 0 0 1 0 0 1 1 b4 0 0 0 0 0 1 0 0 0 1 1 b3 0 0 0 0 1 0 0 0 0 0 1 b2 0 0 0 1 0 0 0 0 0 1 1 b1 0 0 1 0 0 0 0 0 0 0 1 b0 0 1 0 0 0 0 0 0 0 0 1 BRT (V) 0 0.010 0.020 0.040 0.080 0.160 0.320 0.640 1.28 1.8 2.56 X POR Value
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TDA9206
REGISTER DESCRIPTION (continued) Drive Registers (R3, R4, R5) (Video IN = 0.5VPP, Brightness at minimum, Contrast at maximum)
Hex 00 01 02 04 08 10 20 40 80 B4 FF b7 0 0 0 0 0 0 0 0 1 1 1 b6 0 0 0 0 0 0 0 1 0 0 1 b5 0 0 0 0 0 0 1 0 0 1 1 b4 0 0 0 0 0 1 0 0 0 1 1 b3 0 0 0 0 1 0 0 0 0 0 1 b2 0 0 0 1 0 0 0 0 0 1 1 b1 0 0 1 0 0 0 0 0 0 0 1 b0 0 1 0 0 0 0 0 0 0 0 1 CONT (VPP) 0 0.015 0.031 0.062 0.125 0.25 0.5 1 2 2.812 4 G (dB) -30 -24 -18 -12 -6 0 6 12 15 18 X POR Value
Output DC Level Register (R6)
Hex 03 04 08 0F b7 0 0 0 0 b6 0 0 0 0 b5 0 0 0 0 b4 0 0 0 0 b3 0 0 1 1 b2 0 1 0 1 b1 1 0 0 1 b0 1 0 0 1 DC (V) 0.52 0.69 1.35 2.5 X POR Value
Code 00Hex, 01Hex and 02Hex : not to be used
OSD Contrast Register (R7) (VOSD IN = 2.4VMin.., Drive at maximum)
Hex 00 01 02 04 08 0F b7 0 0 0 0 0 0 b6 0 0 0 0 0 0 b5 0 0 0 0 0 0 b4 0 0 0 0 0 0 b3 0 0 0 0 1 1 b2 0 0 0 1 0 1 b1 0 0 1 0 0 1 b0 0 1 0 0 0 1 OSD (V) 0 0.312 0.625 1.25 2.5 4.68 G (dB) -24 -18 -12 -6 0 X POR Value
BP and Miscellaneous Register (R8)
b7 b6 b5 b4 b3 b2 b1 b0 0 1 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 0 1 Function BP Source = HSYNC BP Source = BLK BP Pulse Width = 0.33s BP Pulse Width = 0.66s BP Pulse Width = 1s BP Pulse Width = 1.3s Test Purposes Soft Blanking OFF Soft Blanking ON Semi Transparent OFF Semi Transparent ON Unused X X X X POR Value X
9/12
TDA9206
INTERNAL SCHEMATICS Figure 7
AVDD IN
Figure 8
AVDD
P ins 1-4-7
OS D - BLK - FBLK P ins 2-5-8-13-14
AGND
9206-10.EPS 9206-11.EPS 9206-17.EPS 9206-15.EPS 9206-13.EPS
AGND
AGND
Figure 10
AGND
Figure 9
AVDD 3 (20V)
AVDD
LVDD 9
9206-12.EPS
AGND
6
AGND
Figure 11
AVDD
Figure 12
LGND 10
S DA S CL P ins 11-12
(10V)
LGND AGND
9206-14.EPS
AGND LGND
Figure 13
AVDD
Figure 14
P VCC Pins 17-20-23 AVDD
HSYNC 24
OUT P ins 16-19-22
AGND
9206-16.EPS
AGND P GND Pins 15-18-21
LGND
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TDA9206
APPLICATION DIAGRAM
S YNCHRO EXTRACTO R BLK HSYNC VSYNC 1k 75 47 R GND R 75 47 G GND G 75 100nF 100nF 100nF 1k 100nF 1k 1 2 3 4 5 6 7 8 9 IN1 OS D1 AVDD IN2 OS D2 AGND IN3 OS D3 LVDD HS YNC 24 P VC C 1 23 OUT1 22 100nF BLUE OUT
+12V
47 B GND B
100nF
T D A 9 2 0 6
P GND1 21 P VC C 2 20 OUT2 19 P GND2 18 P VC C 3 17 OUT3 16 P GND3 15 BLK 14 FBLK 13 100nF GR EEN OUT 100nF RED OUT
10 LGND 11 S DA 12 S CL 1k
GND
GND
+5V 1 2 3 +5V 100nF 4 5 6 8MHz 33pF 33pF 7 8 FBLK VSYNC HS YNC VDD P XCK CKOUT XTAL OUT XTAL IN TEST 16
S T V 9 4 2 6
G 14 R 13 GND 12 RES ET 11 SDA 10 SCL 9
2.7k
B 15
100 S DA I2 C BUS 10F 16V 22pF
9206-18.EPS
S CL
11/12
TDA9206
PACKAGE MECHANICAL DATA 24 PINS - PLASTIC DIP
Dimensions a1 b b1 b2 D E e e3 F i L
Min.
Millimeters Typ. 0.63 0.45 1.27
Max.
Min.
Inches Typ. 0.025 0.018 0.050
Max.
0.23
0.31 32.2 16.68 2.54 27.94 14.1 4.445 3.3
0.009
0.012 1.268 0.657 0.100 1.100 0.555 0.175 0.130
DIP24.TBL
15.2
0.598
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No licence is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without noti ce. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1996 SGS-THOMSON Microelectronics - All Rights Reserved Purchase of I2C Components of SGS-THOMSON Microelectronics, conveys a license under the Philips I2C Patent. Rights to use these components in a I2C system, is granted provided that the system confo rms to the I2C Standard Specifications as defined by Philips. SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco The Netherlands - Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
12/12
PM-DIP24.EPS

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